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CMAXQUSB User’s Guide
Table 2. Connector P4 Description (continued)
P4 PIN
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
LABEL
D1
D2
D3
D4
D5
D6
D7
K1
K2
K3
K4
K5
K6
K7
K8
MISO
MOSI
SCLK
CS
OW
—
GPIO DESIGNATOR
K2 when K0 = 1
K3 when K0 = 1
K4 when K0 = 1
K5 when K0 = 1
K6 when K0 = 1
K7 when K0 = 1
K8 when K0 = 1
K1
K2
K3
K4
K5
K6
K7
K8
K11
K12
K10
K9
K15
—
FUNCTION
Memory Data
Memory Data
Memory Data
Memory Data
Memory Data
Memory Data
Memory Data MSB
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
SPI Master-In, Slave-Out (MISO) Data
SPI Master-Out, Slave-In (MOSI) Data
SPI Clock
SPI Chip Select. Configurable active high or active low.
General-Purpose I/O, Maxim 1-Wire Bus
No Connection
*This +12V signal is provided only for legacy systems and is normally unpowered.
Connector P5: JTAG Debug/Programming
Interface
Connector P5 is used during factory test to program the
firmware into the MAXQ2000. This connector pinout is
identical to the MAXQ2000 EV kit, MAXQ2000-KIT. See
Table 3.
Connector P6: Maxim 1-Wire Interface
Although there are currently no mating EV kits that use
this feature, the MAXQ2000’s 1-Wire interface signal
connects to header P6. See Table 4.
Table 4. Connector P6 Description
Table 3. Connector P5 Description
P6 PIN
1
LABEL
VDD
FUNCTION
VDD Power Supply
P5 PIN
1
2, 10
LABEL
TCK
GND
FUNCTION
TCK to MAXQ2000 Test Access Port (P4.0)
Ground Return
2
3
OW
GND
Maxim 1-Wire Interface, Through Level
Translator U6
Ground Return
6
3
4
5
6
7
8
9
TDO
VDDIO
TMS
RESET
KEY
+5V
TDI
TDO to MAXQ2000 Test Access Port (P4.3)
MAXQ2000 VDDIO Power Supply
TMS to MAXQ2000 Test Access Port (P4.2)
Active-High Reset to MAXQ2000
No Connection. Pin is physically removed.
Optional +5V Connection
TDI from MAXQ2000 Test Access Port
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